The present invention relates to a switching circuit, and more particularly to a unidirectional switching circuit capable of performing a high-speed operation.
A field effect transistor (hereinafter referred to as "FET" or "MOS transistor") can act as a switching element which is small in size and low in power consumption, and is suitable for use in a high-density semiconductor integrated circuit. For example, the FET is used as a switching element in a programmable logic array (hereinafter referred to as "PLA"). However, the FET is a bi-directional switching element, and hence it is difficult to form a complicated multi-logic circuit of FET's while satisfying the regularity required for a large scale integration circuit. An example of a PLA using FET's is disclosed in Japanese patent Publication No. JP-A-58-222620. In such an ordinary PLA, one or both of an AND array and an OR array are arranged separately from a main circuit, and an AND operation and an OR operation are performed in the AND array and the OR array, respectively. Since each of the AND array and OR array can perform only a limited logical function, each array is required to have a large number of row lines and column lines each corresponding to a logical product or logical sum, and to provide many of logic circuits externally of the PLA.
While, a static-type semiconductor memory cell including a switching circuit which is made up of an FET and a Schottky-barrier diode, is disclosed in Japanese patent Publication No. JP-A-56-15067. In more detail, the above memory cell includes both a memory circuit formed of a flip-flop circuit, and a Schottky-barrier diode for connecting the memory circuit to a bit line. However, the memory circuit is connected to and disconnected from the bit line, by varying the potential of the ground line of the flip-flop circuit. This ground line is connected to the source electrode of an FET for forming the flip-flop circuit, and hence is connected to an equivalent load which is made up of both a definite input impedance of the FET viewed from the source side thereof and the parasitic capacitance at the above source electrode due to the substrate and gate of the FET. Accordingly, when the memory circuit is connected to or disconnected from the bit line, a large amount of power is required to drive the ground line. Further, the memory cell cannot perform a highspeed switching operation, because the equivalent load circuit has a large capacitive component based upon the above parasitic capacitance, and because the potential of the cathode of the Schottky-barrier diode is controlled through the memory circuit having a relatively high impedance.